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Altera_Forum
Honored Contributor
Honored Contributorthe synthesis of a verilog program
hello all i'm trying to convert my verilog program into a design just to see the circuit how they look like, the whole compilation was successful including synthesis but i couldn't find the corr...
Altera_ForumHonored Contributor
Honored Contributorthx for replying ..now i figured it out..it works now
cheers
