New Contributor
New ContributorHI Frank,
What are the conditions for entering LTD mode?
How to make the rx_is_lockedtoref signal always be 1?
Super ContributorHi,
not sure what you want to achieve. CDR PLL can be either locked to reference clock or data, not both. To receive data, LTD mode must be enabled. User guide describes operation with automatic mode switching:
"The CDR initially locks onto the reference clock, causing it to operate near the received data rate. After locking to the reference clock, the CDR transitions to lock-to-data mode where it adjusts the clock phase and frequency based on incoming data."
New ContributorThe problem I'm having now is that at a serial data rate of 16Gpbs, the locktodata signal is always 1, the locktoref signal is toggle between 0 and 1 , and the link is bit errored. So I want to know if the generation of this bit error is related to the B signal? If it is not related to the B signal, what could be the cause?
The configuration under menu Datapath Options is as follows,
1.Transceiver channel type : GX
2.Transceiver configuration rules : Basic(Enhanced PCS)
3.PMA configuration rules : basic
4.Transceiver mode : RX Simplex
5.Number of data channels : 1
6.Data rate : 16000Mbps
7.Enable datapath and interface reconfiguration : Not selected
8.Enable simplified data interface : Selected
9.Enable double rate transfer mode : Not selected
The configuration under menu RX PMA is as follows,
1.Number of CDR reference clock :1
2.Selected CDR refclock : 0
3.Selected CDR refclock frequency: 100.000000MHz
4.PPM detector threshold : 1000PPM
All other menu contents use the default values.
