Forum Discussion
lancewang
New Contributor
New ContributorThe rx_is_lockedtoref in Native PHY cannot be stabilized at 1
I am using L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP and configured as RX Simplex Transceiver Mode. Select the Enable rx_is_lockedtoref port and Enable rx_is_lockedtodata port in ...
lancewangNew Contributor
New ContributorHI Frank,
What are the conditions for entering LTD mode?
How to make the rx_is_lockedtoref signal always be 1?
FvM
Super Contributor
Super ContributorHi,
not sure what you want to achieve. CDR PLL can be either locked to reference clock or data, not both. To receive data, LTD mode must be enabled. User guide describes operation with automatic mode switching:
"The CDR initially locks onto the reference clock, causing it to operate near the received data rate. After locking to the reference clock, the CDR transitions to lock-to-data mode where it adjusts the clock phase and frequency based on incoming data."
