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Altera_Forum
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19 years ago

The low down on VCCSEL!

Issue# 1 VCCSEL polarity when using DDRII bank voltages. The first issue to be aware of here is that you have to use level shifters to drive the output levels of the FPGA from 1.8 to the 3.3V ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Altera has published 3 known issues solutions to deal with this problem. Also note that the text was originally written for PS and FPP mode but the documentation failed to clarify as such. In PS mode and FPP mode the lower trip point is selected by default independent upon VCCSEL pin setting. Altera is actively working to correct the handbook to minimize the impact to customers.