The low down on VCCSEL!

Issue# 1 VCCSEL polarity when using DDRII bank voltages.

The first issue to be aware of here is that you have to use level shifters to drive the output levels of the FPGA from 1.8 to the 3.3V required by the EPCS device when VCCIO for bank3 is set to 1.5/1.8V. Otherwise you won’t be able to configure your FPGA even though you can program the EPCS device from a blaster. You have to read the latest data sheet closely on this one. Earlier versions of the data sheet did not convey this information.

The Second issue is the incorrect information in the data sheet concerning the VCCSEL pin. In the case where bank3 VCCIO= 1.8v for DDRII support and you are looking to support 3.3V input signaling voltages the datasheet quite clearly tells you to tie VCCSEL to GND (See table Below table 7-6 stratixII datasheet). For the most part this works however there is an underlying gremlin that you have now unleashed by doing this. Some people may never see it but eventually it will bite you. What this does is raise the POR trip point from around 0.9-1.1v to 1.5-2.0v. If you are unfamiliar with the way this behaves over temperature I’ll share the data. As temperature decreases the POR trip point voltage increases until at around 0C the POR trip voltage is around 1.8V. Unfortunately this is the same as what the VCCIO bank voltage is powered at. What you will observe is that the FPGA will not initiate its configuration sequence. This is because the trip point voltage has not been met. This gets a significantly worse when dropping below 0C.

All is not lost though; as the input buffers on the stratixII device are 3.3V tolerant what you want to do is tie the VCCSEL pin to VCCPD although the datasheet states otherwise. There have been requests put in place to fix the documentation so hopefully this will be resolved in the next release of the datasheet for both StratixII and StratixII GX.

Cheers,

Nigel