The Hype of SoC's

I am currently working on a project of real-time multi channel audio processing. Initially this was intended as a pure FPGA-based design, but by mere coincidence I got a Cyclone V eval kit with two ARM cores. Although being early in the process, I gotta tell you that I love this! The power of combining the fast, streamlined, parallel capacity of the FPGA combined with the flexibility and well-known system of Linux SW is just brilliant. In fact, with the combination of the two, the device offers a very simple customer product configuration scheme, using a standard web server running on the Linux part of the device. The SW engineer feels very at home with this.

That being said, I can relate to your co-workers concerns. Getting the FPGA system up and running is pretty straight forward, but getting the SoC HPS system up and running has proven to be far more work than I anticipated. The learning curve is very steep, and there is a lot of do's and don'ts to be learned about this. I have to admit that I also expected the system tools to be slightly more mature. Especially with relationship to software and the process of booting. There exists a number of resources for describing how the configuration and software for boot can be made, but it's a lot of steps and there isn't any ready made automated tools for this (that I know of), so I had to make a custom build framework for this.

I am very positive towards Qsys thou. Doing a system design with a lot of modules, and in my case, IPs that handles streams of data, is extremely tedious and error prone to knit together manually. Qsys makes this process much simpler, and e.g. by adoping the (simple) Avalon-ST interface to your IP, it very easy to do the block-to-block connection configuration in Qsys. You don't have to instantiate any hard or soft CPU in Qsys if its not needed.

I have been working with both dedicated ARM + FPGA solutions in the past and now the SoC FPGA solution. The advantage with the HPS solutions is the ease of interfacing between the CPU and the FPGA. E.g. you don't have to bother with PCIe. The downside is that very much is configurable, which requires both the FPGA engineer and the SW-engineer to work in a completely new way of thinking. It's no longer "what can we do with the peripherals we have", but rather "what do we need". And that is were it gets complicated. You need to know how you want to build your system, including the SoC system parts. And that can be a lot to absorb.

All in all, I expect to end up with slightly more engineering hours on FPGA and HW, but I'm hoping it will be shaved off from SW as standardized interfaces/drivers can be used. We'll see, the project is far from complete...

Well, these are my thoughts. Hope it helps your considerations.