The end of AHDL?

Im pretty sure they will continue supporting AHDL, just with the removal of the Quartus simulator (much reduced in functionality compared to modelsim) you will no longer be able to simulate raw code - you will have to simulate netlists which is slow and not what you want to do if you're trying to test functionality rather than timing.

AHDL isnt much more than a netlist language anyway, and being proprietry, Im glad this will hopefully put people off using it and using much better languages (VHDL or Verilog) instead. In addition, graphical entry can be useful, but again you're constrained by its limitations.