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Altera_Forum's avatar
Altera_Forum
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13 years ago

the beginning of the my adventure with FPGA

hello every one i'm completely new in field of FPGA and VHDL or VERILOG programming... plz can some one tell me which one is worth to learn VHDL or VERILOG? any video tutorials or some useful ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

As a C programmer, you will probably prefer the syntax of verilog (as it was kind of based on C). VHDL can really annoy C programmers as it has strict typing. There are pros and cons for each but at the end of the day they can both produce the same hardware. There is a big push for system verilog from the verification point of view, but you can do a lot of things with pure VHDL, that I dont think many people realise.

Im a VHDL guy, and havent read any books, so I cant recommend any, but Pong Chu's book does come up alot, even though he does push his opinion as "best practice" in at least 1 case.