Forum Discussion
Altera_Forum
Honored Contributor
13 years agoTo add a little info to your original question:
Verilog is a flexible language. It is easy to work with when switching between types (integers vs vectors). VHDL is a bit more strict, but has some added features that can be helpful for more advanced users (generics and bound integers). From my experience, both VHDL and Verilog are widely used. I will admit that I have not found a Verilog book I like yet. My personal favorite VHDL book for beginners is "VHDL : Programming By Example" by Douglas Perry. Bertulus recommended "RTL Hardware Design using VHDL" Pong. Chu. This book is a bit harder of a read. I do highly recommend it for more advanced VHDL programmers though.