The altera dual-port ram timing error

Question

When I use the altera dual-port ram in our product, the dual-port ram is right in emluator.but, I download the source code to the altera FPGA，the timing of the dual-port ram is wrong,the readdata delay one clock. The picture 111 is in the emluator

The picture 2222 is in the SignaltapII .

altera_forum · Answer

where is your code?

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The altera dual-port ram timing error

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