Altera_ForumHonored Contributor14 years agoThe altera dual-port ram timing error When I use the altera dual-port ram in our product, the dual-port ram is right in emluator.but, I download the source code to the altera FPGA,the timing of the dual-port ram is wrong,the readd...Show Moremultiple-attachments.zip8 KB
Recent DiscussionsFeasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LPQuestionWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply DevicesSolvedAvalon-ST configuration with Agilex 3 fails