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Altera_Forum
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18 years ago

Testing of internal resources

Does anyone have a simple code set for testing internal FPGA resources to aide in creating a BIST type test methodology. Something like a LUT based Pattern generator, the block to be tested (LU...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The CRC_ERROR is available in Stratix and later FPGA devices. It is useful for checking the CRAM bits (Configuration data in the device). So knowing that Altera devices are 100% tested and that the device is still correctly configured if CRC_ERROR pin is not flagging an error should be good enough.