TCP Ethernet packet in FPGA?

The TCP protocop is typically handled by software. It's so complicated to do in hardware that you'd need a really good reason to do it in hardware. If you want to send or receive lots of data directly to a block of hardware and can live with packet loss or reordering UDP is a much simpler alternative.

To answer your question, you must start by reading the datasheet of the component you need to connect to. You'll find information on how to use the control signals, and often some waveforms. From there you can write your module, a test bench that simulates the component, and test your code. Once it's working you can try and put it in the FPGA.

I think you should see some tutorials about QSys and Avalon interfaces too. You'll learn how to add a processor to your system, connect different modules together and make your own modules. Depending on the SSRAM it may be just enough to add a "Generic Tri-State Controller" IP module to your system in QSys and connect the SSRAM directly to it.