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Honored Contributor
Honored ContributorTCP Ethernet packet in FPGA?
Hi, I have a Cyclone IV GX transceiver kit. I want to observe TCP packets in signal tap in FPGA (and hopefully it'll be same as the one I observe in Wireshark) How do I do that? This is wh...
Altera_ForumHonored Contributor
Honored ContributorIf you are using the Altera Triple Speed Ethernet IP, the received packets come out in an Avalon Stream Source. You can include all the signals from this analog interface in the signaltap project, and use a conditional storage qualifier with both the ready and valid signals at 1. That way signaltap will only record the signals when there is an actual transfer taking place. Then add a trigger on the "start of packet" signal.
