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Altera_Forum's avatar
Altera_Forum
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16 years ago

SystemVerilog Testbench

Hello, I'm reading the book SystemVerilog for Verfication by Spear and was wondering if anyone is using SystemVerilog for Verfication and if they had an simple example they could provide? Thank...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

No, all those files are just necessary if you want to have complex testbenches based on the methodology described in that book. Other books have other methodologies, most of them with a single file and module.