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Altera_Forum's avatar
Altera_Forum
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16 years ago

SystemVerilog Testbench

Hello, I'm reading the book SystemVerilog for Verfication by Spear and was wondering if anyone is using SystemVerilog for Verfication and if they had an simple example they could provide? Thank...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I hope someone can help. I've been using the simulator built into Quartus so writing test benches and running ModelSim is still new. When I think of a test bench I usually see a single file but as I look into SystemVerilog Verification it mentions the Generator, the Agent, the Driver, the Monitor, checker. All of which are in separate modules and appear to be separate files too. Is that a big deal?

I run ModelSim from Quartus.

http://chris.spear.net/systemverilog/

The web site above has some examples that I'll try to get working.

joe