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Altera_Forum
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16 years ago

System verilog (general info)

quartus9.1 support SystemVerilog, does anyone know how the SystemVerilog assertions are processed when synthesisin Thanks in advance for helping, Best regards Jenny teh
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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No, they are gracefully ignored.

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Yes, that's the way most of the SYNTH tools behave. This is really useful for RTL designers as they can now comfortably add assertions during their RTL coding stage itself without worrying about extra gatecount, tool issues, additional need for ifdef etc. A while back the formal equivalence checkers didn't support these, but now they do is what vendors tell me!

Srini

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