Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

System verilog (general info)

quartus9.1 support SystemVerilog, does anyone know how the SystemVerilog assertions are processed when synthesisin Thanks in advance for helping, Best regards Jenny teh
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

No, they are gracefully ignored.