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Honored Contributor
Honored Contributorsystem verilog "enum" and scope
I am using system verilog's "enum" construct to define the states of 2 state machines I have in my module. For example: line num 50: enum logic [1:0] {INIT, WAIT, RUN} state_1; …. line num ...
Altera_ForumHonored Contributor
Honored ContributorI'm pretty sure the synthesis tool treats the named values of the enumeration as constants. So it is like declaring the constant INIT twice.
