system verilog "enum" and scope

I am using system verilog's "enum" construct to define the states of 2 state machines I have in my module. For example:

line num 50: enum logic [1:0] {INIT, WAIT, RUN} state_1;

….

line num 100: enum logic [1:0] {INIT, COND1, COND2} state_2;

I get the following error in synthesis:

Error (10149): Verilog HDL Declaration error at <file_name>(100): identifier "INIT" is already declared in the present scope

RivieraPro is complaining about this as well.

I know I could do this with VHDL's "type" construct.

First of all is the synthesis tool interpreting this correctly? If so (lame) then is there a way I could declare these 2 states such that they fall in different scopes within the same module?