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Altera_Forum
Honored Contributor
Honored ContributorSystem to read a RAM memory on FPGA
Hello,
I am developing a module of hardware of a robot for educational application and I have some problems. I developed a serial interface of the FPGA with a microcontroller utilizing the protocol RS232. The data received by the serial interface should be writing in the RAM memory and then well-read by some system that I do not know for control dc motors and read sensors. What should I do for to write those data in the RAM memory and read them? :confused: The block diagram of hardware structure is below. At once I thank for the attention! http://images.orkut.com/orkut/photos/OgAAAPE8DuYtNOJ861I44qzk9YSUusEEi2ZTl49YNpFTE-HP6awjMaoxCTiMM_C-U77kyyCm8x3bprSRjF3I7HikGkUAm1T1UGYKHpp20gsGTLS3Z7K8GYnMGCB8.jpg7 Replies
Altera_Forumok, thank you so much!
- Altera_Forum
This project is called "Zet PC platform" and it runs Windows 3.0 sorry
Opencores has a link to this web page... http://zet.aluzina.org/index.php/pictures (http://zet.aluzina.org/index.php/pictures) There are so many things possible with FPGA ( like the good old C64 with 1541 Floppy Disk emulation but thats a different link ) - Altera_Forum
How there is a project that has a complete pc with bios and vga inside a fpga that runs windows 3.1??
- Altera_Forum
if you want to use a free soft core cpu, have a look at opencores.org there you can get lots of cpu's. for example if you are familiar with the 8051 just get such a 8051 cpu source code and build you own system inside the fpga.
btw .. there is a project that has a complete pc with bios and vga inside a fpga that runs windows 3.1 - Altera_Forum
You can have a look at the various Nios II tutorials
- Altera_Forum
thanks for your reply, but how can i develop a soft core CPU in FPGA?? and where can i get this?
- Altera_Forum
Do you intend to use a soft core CPU in the FPGA, or do you plan to do everything in hardware?
If you do everything in hardware I think that you can store the data in registers. They are directly readable/writeable in VHDL/Verilog.
