Forum Discussion

SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Hi all, The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge. Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven fr...
Programmable Logic Device
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi SYiwe ,

1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source.
>> Yes, it shall be independent and free running

2、If the answer of above question is positve, how should I debug to make the System PLL work?
>> did you compile the design ? is it running full compilation without any issue ?
>> IF yes, please tap a signaltap , or you may use lspci to check either the ltssm is able to link up or not/
>> Next, which design that you are using ? is this custom design or from our design example - I suggest to try direct the design example from Quartus IP catalog

Sorry for late reply due to Lunar New Year holiday, Happy New year to you as well.
Looking forward to hear back from you.

Regards,
WincentChiah_Altera

SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Hi Wincent，

Thank you for your reply, wish you happ new year.

  1. The design is a full compiled Agilex5 PCIE example design,
  2. A signal tap is instanced and I found the system PLL cannot be locked with signal tap,
  3. I've used lspci and no FPGA PCIE EP found,
  4. Please let me know if you have any more suggestions. 

 

Regards.