Forum Discussion

SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Hi all, The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge. Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven fr...
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 month ago

Hi,

PCIe reference clock is spread spectrum modulated on most system boards, this may cause locking issues. PCIe IP core PLL should have bandwidth settings that tolerate spread spectrum clocking, but system PLL probably has not. To check if the issue is related to spread spectrum clocking, you can disable it in BIOS setup.

Regards Frank

  • SYiwe's avatar
    SYiwe
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Hi Frank,

    Thank you for your reply.

    1. How Can I confirm whether system PLL support spread spectrum modulated reference clock or not? I read PCIE IP and Native PHY user guide but no relative information found. 
    2. Do you mean that I can try to disable PCIE card edge reference clock spread spectrum modulated function in BIOS when the main board linux system start up?

    I will be appreciated if you can show me more suggestions, regards.

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      1 month ago

      Hi SYiwe,
      system PLL has usually low bandwidth setting while PCIe PLL is set for wide bandwidth. My understanding is that wide bandwidth setting is necessary to support spread spectrum reference clock. You may try to change system PLL setting also to wide bandwidth and check if it will lock then.

      Regards
      Frank