System Library Properties

Hi,

Thank you for answering. I chose the followings :

PLL clock frequency : 90MHz

Memory clock frequency : 100MHz

Local interface clock frequency : Full

On the slide PHY settings, I have a clock phase of 90.

Then, I included the file ddr_sdram_phy_ddr_timing.sdc (which is generated by sopc if I'm not mistaken) to the project.

What should I change ?

Myriam

PS : I have a Cyclone III EP3C25