system console, external memory, multiple masters

Also, here is part of my top level code: just the mem pins and the instantiation

//generated from terasic system builder ....

//////////// LPDDR2 //////////

output [9:0] DDR2LP_CA;

output DDR2LP_CK_n;

output DDR2LP_CK_p;

output [1:0] DDR2LP_CKE;

output [1:0] DDR2LP_CS_n;

output [3:0] DDR2LP_DM;

inout [31:0] DDR2LP_DQ;

inout [3:0] DDR2LP_DQS_n;

inout [3:0] DDR2LP_DQS_p;

input DDR2LP_OCT_RZQ;

.....heres my instantiation

spiFromQsys8Bits u0 (

.clk_clk (CLOCK_125_p), // clk.clk

.reset_reset_n (1'b1), // reset.reset_n

.spi_0_external_MISO (GPIOSPIGPIO[3]), // spi_0_external.MISO

.spi_0_external_MOSI (GPIOSPIGPIO[2]), // .MOSI

.spi_0_external_SCLK (GPIOSPIGPIO[1]), // .SCLK

.spi_0_external_SS_n (GPIOSPIGPIO[0]), // .SS_n

.memory_mem_ca (DDR2LP_CA), // memory.mem_ca

.memory_mem_ck (DDR2LP_CK_p), // .mem_ck

.memory_mem_ck_n (DDR2LP_CK_n), // .mem_ck_n

.memory_mem_cke (DDR2LP_CKE), // .mem_cke

.memory_mem_cs_n (DDR2LP_CS_n), // .mem_cs_n

.memory_mem_dm (DDR2LP_DM), // .mem_dm

.memory_mem_dq (DDR2LP_DQ), // .mem_dq

.memory_mem_dqs (DDR2LP_DQS_p), // .mem_dqs

.memory_mem_dqs_n (DDR2LP_DQS_n), // .mem_dqs_n

.oct_rzqin (DDR2LP_OCT_RZQ) // oct.rzqin

);