Synthesis side effect between independent components

First, when doing STP signals are your refitting the full design(rather than just incrementally fitting SignalTap)? My guess is yes.

Most likely, your first component is not fully constrained for static timing analysis. Note that if you rerun the fitter, you get different timing on everything in your design. Now, if it is fully constrained, every new fit will either tell you if it passed or failed your required timing. But without a fully constrained design, the fitter can blindly make changes without ever knowing if it makes your design better or worse. How many clock domains are in your system? How are they related? How do you transfer between domains? How do you interface with the outside world. Does every IO have a Tsu, Th, Tco and min Tco constraint if you're using the Classic Timing Analyzer, or does every IO have a set_input/output_delay with constraints for both -max and -min?

Note that there are designs out there that are not fully constrained. Sometimes it's the user just hoping it works and they luckily get by. But more often its someone who fully understands what the the Th constraint on the IO means, and realizes they have externally balanced the clock tree, making a Th violation impossible. If this doesn't make sense, please go over the timing analysis documentation and feel free to ask more questions. Timing analysis is a topic many people want to ignore, or keep as simple as possible, when it's really a very, very complex subject.

(And if this isn't a timing issue, which I can't be positive of from the description, then you just got a nice rant you can ignore...)