Yamada1
Occasional Contributor
Occasional ContributorSynthesis results and different behavior
I made an SPI interface circuit, but the SCLK output is always 'H' and it doesn't work. It would be helpful if you could give me some hint to solve it. The survey results are as follows. 1) MOSI...
1) Yes. There are many VHDL attributes like this. Just googled this: https://redirect.cs.umbc.edu/portal/help/VHDL/attribute.html
2) Not sure what you mean here, but if your clock is not coded correctly, then nothing is going to work correctly because it will never get to the if checks.
3) rising_edge is part of std_logic, so as long as you're using that library, it will work and is recommended.
