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Altera_Forum
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16 years ago

Synthesis ramstyle

Hi, I am trying to do the ram code but failed to infer to Mlabs, which instead goes into logic. Can anyone help? I attached the source code. device used:STRATIX V GT Thanks a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The point is, that Stratix IV and some other FPGAs are supporting asynchronous read. In so far, you can wish Quartus to infer asynchronous read for internal RAM. But I fear it doesn't. I didn't perform any tests, but if you see, that using sync versus async read makes the difference, it's apparently unsupported.