Synthesis ramstyle

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Hi,

I am trying to do the ram code but failed to infer to Mlabs, which instead goes into logic.

Can anyone help? I attached the source code.

device used:STRATIX V GT

Thanks alot for helping.

Best regards

Jenny

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Hi,

the RAM is implemented in logic, because you are using a asynchronous read. I would follow the advice of FvM and use the megawizard instead inference, because you have a better control over the implementation. However, the following example shows a that the inference in MLAB in principle works.

(* ramstyle="MLAB" *) module test(clk1, we, data_out, rdaddr, wraddr, datain);

parameter addr_width = 6;

parameter data_width = 10;

input clk1,we;

input [data_width-1:0] datain;

input [addr_width-1: 0] wraddr,rdaddr;

output [data_width-1:0] data_out;

reg [data_width-1:0] q; reg [data_width-1:0] mem [(2**addr_width)-1:0] /* synthesis syn_ramstyle = "MLAB"*/;

always @(posedge clk1) begin

if (we) mem[wraddr] <= datain;

end

always @(posedge clk1) begin

q <= mem[rdaddr];

end

assign data_out = q;

endmodule

Kind regards

GPK