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Altera_Forum's avatar
Altera_Forum
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15 years ago

Synthesis error - RAM resource ?

Dear all, Currently I'm designing a project using Stratix IV 4SGX230N. In my design I try to implement three FIFOs (all of them are designed using MegaWizard) which resource usage are shown in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Update :

I found some mistakes in my FIFO depth. I have re-compiled and synthesized my design successfully.

@Tricky :

If you don't mind I'm still waiting for your explanation about memory efficiency. Thanks :)