Honored ContributorDear All,
is is possible to create a synchronous process reacting on both clock edges? Is it synthesized? Or I have to use PLL to go for twice higher clock frequency and use only rising_edge? thanks da.
Honored ContributorHi,
no, a process that is sensitive to both edges cannot be synthesized, at least not in a FPGA. The general solution would be to use a PLL. Of course, in some application cases you can get the job done by using two different processes on the two clock edges. The most relevant case is DDR I/O.Honored Contributoroki. PLL rulez then.
Thanks for quick reply. d.
