Synchronous Design Timing (VHDL)

Thanks a bunch for the responses. I had some time to play around with ModelSim and the DCFIFO and I've noticed that there's a one cycle delay from when the simulator wave shows a change in the signal and when my component can see that change.

Example as seen from ModelSim:

-After adding a byte to the FIFO, 'fifo_e' goes to '0' (i.e. no longer empty)

-One cycle later my VHDL code sees that change and sets 'rdreq' to '1'.

-One cycle later DCFIFO sees my request and outputs the next word.

-One cycle later that word is now finally visible to my VHDL piece.

So it seems that after I assert 'rdreq', I need to wait two cycles before reading from the FIFO's data out.

Does that sound correct? So: "Changes made to a signal on the rising edge by component A aren't noticed until the next rising edge of component B".

That makes sense to me at least (as it avoids the race condition thoughts that pop into my head). I haven't had a chance to look at the TimeQuest stuff yet, so if I'm way off in the above statements, then that might clear everything up.

Thanks again!