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a). Assert 'rdreq' on the rising edge and read on the next rising edge?
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Yes.
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If we're both working on the rising edge, am I guaranteed that my signal changes will be in effect when the FIFO processes its input? I'm worried about timing/delays.
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Short answer: Yes.
Slightly longer answer:
You need to set proper timing constraints. Ie, set the clock's period. Take a look at TimeQuest's user guide.
If you set you timing constraints properly, the tools will take care of all the delays within the FPGA and try (very hard) to ensure that the timings are met while syntethizing your VHDL/Verilog code.
If they aren't able to, the tools will tell you that timing constraints were not met.
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