Synchronizing TXCVR & RXCVR

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I am using the Cy IV.

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I assume you mean Cyclone IV GX.

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I instantiated transceiver with Automatic synchronization . I see the pattern signals indicated the K28.5 coding correctly .. they came h9CBC, BCBC. I figured this happens sometimes after the RX reset is de-asserted.

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Depending on the IP core you use, its up to you to supply the correct reset sequence, so there should be no "I figure ...", you should know when it is supposed to happen :) But yeah, once the receiver CDR locks and it transitions to lock-to-data mode, it should start synchronizing.

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1- If the transmitter is up an running, when should it start sending real data

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The transmitter can send data whenever it likes. Whether or not the receiver at the other end is listening is another thing ...

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2- Since the FPGA FSM transmitter side is sending "something" on every clock cycle while the synchronization is detected by the RXCVR and after when does the transmitter start sending real data? How does the FPGA FSM know the beginng of real data vs the "filled data" that was sent until synchronization ocurrs? I assume at this point a protocol with beginning or frame or something needs to be detected as well and then every clock cycle is valid data until some kind of "end of frame"? (based on some type of protocol I assume)

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Yes, it depends on the protocol. In basic mode, you have to define the protocol.

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2- In fig 1-23 the byte order is shown misaligned but the byte ordering block that follows should put the data back into the same byte ordering as the transmitter (correct?)

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Yep. Depending on the ALTGX setup, you can access this signal manually, or the IP core wrapped over the ALTGX might use it to get data aligned correctly.

Simulate the ALTGX component and you'll get a better feel for how things work.

Cheers,

Dave