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Altera_Forum's avatar
Altera_Forum
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12 years ago

synchronization problem

Hi , i have a digital card with FPGA and the FPGA transmit serial data from the pin from this card to other external loopback card(connected together) and then the data back to the the FPGA to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi ,

The data rate i'm sending is at 25Mhz - it is PRBS data (serial data) .

As I understood your explanation , I need to detect the first start edge (because i generate it , i know when it start ...) and thens ample at High speed clock -

lets say 100MHz until the higher clock is in the center of the data to be able to sample at the healthy and stable signal, and then sample at 25MHz again

to reproduce the original data at 25MHz .

am i correct ? will it work stable ?