synchronization problem

What is the data rate you are sending at?

There are several different methods that can be used, but each have their own issues: Like you said the start/stop bit of RS232 adds overhead, but it allows you to align each byte. This works well in modern FPGAs with data rates up to 1 Mbps. If you know the transmit data rate, you just simply detect the first start edge, then count your high speed clocks until you are in the center of the bit, to sample, and then sample at the low speed data rate until you receive a byte (or n Bytes) (You don't have a clock to adjust the phase, because you are assuming your clock is a high speed internal clock.)

Manchester Encoding allows you to recover the sending clock. But usually you need a preamble of some known pattern to define the "Start" of a packet. (So you can determine if it's a 1 or a 0)

There are other methods as well, but these are the simplest.

Pete