Honored ContributorThinking about switch to Altera device from Xilinx. But current design is heavily using the XPM for CDC and infer memory (not ultra-ram). So would like to check if Altera has anything similar or any easy solution for this?
Thanks.
Honored ContributorRAM inference is quite robust in both tools, so I don't suspect a problem. If you are using unique cases(like embedded ECC), then inference won't work and you need to instantiate the IP Variant, but for most cases it works fine. If you open a VHDL/Verilog file in Quartus editor, go to Edit -> Insert Templates and you can find many full RAM inference examples. You want yours to just convert over, but if for any reason they don't this is a good place to look.
I'm not familiar with XPM. Is it a macro for domain crossing? Is it to reduce metastability, or some more like IP that does handshaking/FIFO/etc. to cross domains? Naturally, Altera customers cross clock domains in pretty much every design, so it's by no means a roadblock, but it might be a different methodology.Honored ContributorThanks for the reply. Where can I find related documents?
--- Quote Start --- RAM inference is quite robust in both tools, so I don't suspect a problem. If you are using unique cases(like embedded ECC), then inference won't work and you need to instantiate the IP Variant, but for most cases it works fine. If you open a VHDL/Verilog file in Quartus editor, go to Edit -> Insert Templates and you can find many full RAM inference examples. You want yours to just convert over, but if for any reason they don't this is a good place to look. I'm not familiar with XPM. Is it a macro for domain crossing? Is it to reduce metastability, or some more like IP that does handshaking/FIFO/etc. to cross domains? Naturally, Altera customers cross clock domains in pretty much every design, so it's by no means a roadblock, but it might be a different methodology. --- Quote End ---Honored ContributorThis is for RAMs:
https://www.altera.com/en_us/pdfs/literature/hb/qts/qts_qii51007.pdf
