Support for true LVDS or emulated LVDS output

Most mid to high end CPLD and FPGA devices support LVDS I/O at this point.

The MAX V is still in active production, but like all FPGA/CPLD devices now is severely supply constrained.

Lead times are out in the 6 mos to 12 mos time frame. Pretty much for any device from any vendor.

Bigger (and smaller) MAX V devices exist, some with compatible I/O footprints.

One time programmable CPLDs and FPGAs are not a thing anymore. Haven't seen one in a long time.