Forum Discussion
7 Replies
- Altera_Forum
Honored Contributor
what kind of fmax and latency/pipeline requirements do you have? and what is the target device?
- Altera_Forum
Honored Contributor
The target device is a Stratix II.I want it to use as less as possible resources because i have to compute it many times.
- Altera_Forum
Honored Contributor
The thing that i care most is to be synthesizable if this helps.
- Altera_Forum
Honored Contributor
you can use one instant of parallel_add to sum up all your inputs. see megawizard(arithmetic section)
- Altera_Forum
Honored Contributor
Could you please be more specific because i am new to this stuff.Thanks again
- Altera_Forum
Honored Contributor
Ok, go to quartus tools menu then megawizard plug-in manager and choose
parallel_add from the arithmetic group. Then set your parameters e.g. bit width, number of inputs, size of output, pipeline stages. Thats all. then you get the adder component , just connect it in your project. If the number of inputs allowed in your case is < 40 then you can use two instants... - Altera_Forum
Honored Contributor
Hmm. The Stratix II is able to add three numbers per ALM-chain, right? If you build a trinary tree (which I suppose parallel_add will use), you will get a depth of 4 stages. Because of that I suggest you use 1, 2 or 4 pipeline stages (where 4 allows the highest clock frequency).