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Altera_Forum
Honored Contributor
Honored Contributorstratix5 PLL minimum input clock speed
What is the minimum input clock speed for Stratix V device? I have a 10 MHz clock that I can input into the device. I want to use a PLL to multiply it up to 160 MHz for use in the core. Can Stratix V do it?
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Altera_ForumAccording to the megawizard, 5-800 MHz are valid input frequencies, and the 10 MHz source with 160 MHz output is valid.
I would still put it in a temp design and compile it first however, sometimes you get warnings that may not show up in the megawizard. Pete
