Stratix3 DPA jitter timing

I'd like to send data between S3 parts using LVDS channels with DPA.

I see in the ALTLVDS megafunction user guide how to calculate RSKM when not using DPA, but the manual says "In DPA mode, use DPA jitter tolerance instead of RSKM".

I'm receiving data generated by an ALTLVDS transmitter in another S3 part.

How can I determine clock jitter on transmitter side, and how does this relate to DPA jitter on the receive side?

Presumably the DPA clock input jitter is a function of transmit clock jitter plus jitter from the PLL that spins the input clock up to the bit clock for the DPA.

Any doc or info on this? Many thanks...