Occasional Contributor
Frequent ContributorHi allen18,
May I know if you are using the Altera Dev Kit? https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html
Could you please share the schematic file you are referring to?
Thanks.
Best Regards,
Ven
Occasional ContributorHi ventt,
I'm not using DEV kit.
I cannot provide a complete schematic file but I can confirm that both reference clocks are valid and that the PCIe pin connections are correct, because when using the first set of reference clocks, DMA data transmission and reception can be performed normally.
In UG, it can be seen that when using an independent reference clock, the slot clock configuration should be set to OFF, but I do this, the situation did not change much.
When I use the second set of parameter clocks, PCIe cannot establish a link, and ltssmstate changes between 2 and 3 several times, eventually staying at 2.
