Forum Discussion
mappy5
New Contributor
New ContributorStratix10 Global Clock assignment is ignored
I'm trying to synthesize an IP using virtual pins.
The Clock signal of the virtual pin is directly connected to the IP.
Global Signal ON is set in the assignment editor for the clock of the virtu...
SyafieqS
Super Contributor
Super ContributorGlobal Signal assignments only controls whether a signal is promoted using the specified dedicated resources or not, but does not control which or how many resources are used.
To take full advantage of the routing resources in a design, make sure that the sources of clock signals (input clock pins or internally-generated clocks) drive only the clock input ports of registers
mappy5Hi SyafieqS_intel,
Will assigning a virtual pin to a dedicated CLK pin solve the problem?
Is the GCLK allocation method different between Stratix10 and Arria10 due to the difference in clock resources?
