Stratix V Transceivers in Qsys

Hi I did a simple transceiver project in Qys running at 1250Mbps. I have generated the Verilog code for the design and programmed the device. However, I have trouble establishing a link in the system console to run the BER and EyeQ analysis. The FPGA used is 5SGXEA7N2F45C2ES and version of Quartus is 12.0. Attached are some pictures related to the project. Would really appreciate it if anyone could help me figure out what is wrong. Thanks.