New ContributorStratix SDM Encryption Accelerator?
The Stratix 10 white paper states that HW based cryptography acceleration is available through the SDM mailbox mechanism. However, I cannot find any documentation or code that describes such. Where can I find further details?
The SDM uses these blocks during the configuration (and reconfiguration) process; however, these acceleratorblocks are also available for user applications after device configuration with appropriate licensing through the Intel Quartus® Prime software. For example, designs could use these blocks for encryption/decryption of data traffic in user applications, as well as authenticating messages to and from the FPGA. Service requests to these blocks come through either the FPGA fabric or the ARM* Cortex*-A53 HPS system to a request mailbox in the SDM, which instructs the blocks to perform encryption, decryption, hashing, signing, or signature checking functions.
I cannot find any reference to this functionality in either the "Intel® Stratix® 10 Device Security User Guide" nor in the "Mailbox Client Intel FPGA IP User Guide".
