Forum Discussion
Hi LowLevelGuy,
Can you provide the link of the white paper?
Regards,
Fakhrul
Sorry, I missed your reply as all of Intel's emails are considered Junk by Office365.
This is the whitepaper. See page 2, "Encryption Support Hardware".
All I want to do if to find out how to use the stated features as no public documentation exists for them.
https://cdrdv2-public.intel.com/650483/wp-01252-secure-device-manager-for-fpga-soc-security.pdf
Excerpt below, (emphasis added):
The SDM uses these blocks during the configuration (and
reconfiguration) process; however, these accelerator
blocks are also available for user applications after device
configuration with appropriate licensing through the Intel
Quartus® Prime software. For example, designs could use
these blocks for encryption/decryption of data traffic in user
applications, as well as authenticating messages to and from
the FPGA. Service requests to these blocks come through
either the FPGA fabric or the ARM* Cortex*-A53 HPS system
to a request mailbox in the SDM, which instructs the blocks
to perform encryption, decryption, hashing, signing, or
signature checking functions.