Stratix IV FF Sync V/s Async Clear

Yes.

One thing I like to look at is the Fitter Report -> Resource Utilization -> Control Signals. I then sort on the Usage column. You may code your reset for the asynchronous clear, but you'll see the design is full of synchronous clears too. This means synthesize was able to take your general RTL and target the synchronous clear port of the register/s, thereby making a more optimal area and performance design. The difference isn't huge, but it's not in the noise either. (It's also interesting to look at clock enables, as most designs have a ton that were never explicitly coded for)