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Honored Contributor
Honored Contributorstratix III with DDR2 temination
hi my design include stratix III device with 2 ddr2 hp core. each core is facing 5 DDR2 components when 1 of the 5 is for ECC. i looked at the termination schemes in AN408 and not found my ans...
Altera_ForumHonored Contributor
Honored ContributorAN408 has been updated and is now considering also Stratix III/IV ODT. I understand from AN408 and Stratix III Device Manual, that DDR2 data lines are operated without external resistors at the bus. For the address and control lines a parallel termination (at bus end) is necessary. The DDR2 I/O standars is SSTL-18 anyway.
It's also meaningful to my opinion to consult memory vendor design guides, e. g. from Micron. They are usually assuming a state-of-the-art memory controller, that have ODT as Stratix III has. Regarding your calculation of disspated power, how many data lines do you have?
