stratix III with DDR2 temination

AN408 has been updated and is now considering also Stratix III/IV ODT. I understand from AN408 and Stratix III Device Manual, that DDR2 data lines are operated without external resistors at the bus. For the address and control lines a parallel termination (at bus end) is necessary. The DDR2 I/O standars is SSTL-18 anyway.

It's also meaningful to my opinion to consult memory vendor design guides, e. g. from Micron. They are usually assuming a state-of-the-art memory controller, that have ODT as Stratix III has.

Regarding your calculation of disspated power, how many data lines do you have?