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Altera_Forum
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16 years ago

Stratix III: Problem with Row I/O CLK2p ... output

Dear all I'm trying to output a clock on the combined "Row I/O, CLK2p, DIFFIO_RX_L15p, DIFFOUT_L29p" pad "U28" on my Stratix III EP3SL70 device. Although Quartus notes no problem, the p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Problem solved!

I found out that the signed-off documents (schematic/layout) do not match with what the board suppliert delivered (by measuring on an unassembled board i got recently). The pin in question was simply not connected.

Thanks anyway for the help trials... ;-)