Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Stratix III: Problem with Row I/O CLK2p ... output

Dear all I'm trying to output a clock on the combined "Row I/O, CLK2p, DIFFIO_RX_L15p, DIFFOUT_L29p" pad "U28" on my Stratix III EP3SL70 device. Although Quartus notes no problem, the p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Already tried this, and I was not able to read the input (and the signal was reportedly there on the net...). Actually, the behaviour is the same on several boards, and a test with external pull-up / pull-down resistors showed different behaviour with the pin used as FPGA input and output, so I don't expect any soldering or conectivity problems on my boards...