Thanks Rysc,
Speed grade C4 (not an option to move up).
Its the read side
....altsyncram_component|altsyncram_t2t1:auto_generated|rdaddr_reg[2] to
....altsyncram_component|altsyncram_t2t1:auto_generated|dataout_latch[1]
The memory is 272 deep by 8 wide so (due to the changes to the MLAB spec) will require 17 MLAB blocks I believe. This is why I was wondering if it was to do with delays caused by fragmentation.
M9K is an option but I'm trying to balance my RAM usage and keep the memory efficiency as high as possible. I may have to do that if nothing else works, but i suspect the problem will just pop up somewhere else later on, so if there's a neat fix now it will help.
I'm a bit depressed because all the fitter physical synthesis options returned 0 or <20pS improvement - sounds like I've hit the end-stops on this. I may have to resign myself to using more M9Ks.
Thanks again,
Dave.